Open Architecture ATE and 250 Consecutive UIs

Problem Statement. A very different way is needed to perform jitter testing of multi-Gbps physical layer ICs on a highvolume production line [1]. To perform high-volume production testing, several issues must be addressed. First, what measurements are required to characterize jitter in multi-Gbps physical layer ICs? Should the BER performance of the IC be tested or not? Secondly, as shown in Figure 1, the PCI Express standard defines an eye diagram test for receivers (RX) [2]. Is an oscilloscope sufficient for production test with respect to a test time and the required accuracy of BER < 10? In fact, the data recovery architecture which is implemented in the IC under test should determine the type of measurements required. Which Architecture? In a multi-Gbps physical layer IC, the key measurement is the timing misalignment between an incoming bit sequence and a sampling clock. It follows that edge fluctuations in the bit sequence and the clock should be measured. Is a jitter tolerance test required? If the IC implements data recovery by combining a phase detector and a charge pump to provide integrated sampling phase error to a VCO, the answer is yes. Due to the PLL-dependent architecture, it requires a jitter tolerance test. However, the less the BER threshold becomes, the longer the test time it requires. Thus, its test time prevents it from being used in the production line. Instead, a new method is required and one was proposed, which can perform the test with a 10X reduction in test time [3]. On the other hand, if the IC recovers data by oversampling each serial bit using sampling clocks provided from a VCO, with the sampling frequency controlled by an external reference clock, the answer is no. Since the oversampling provides M samples of each bit, the timing misalignment between a bit sequence and an oversampling clock is relaxed and jitter is reduced to the random jitter associated with the bit stream. In this case, it is sufficient to measure the RMS value of the input timing jitter at the RX package pins.